Reader discussions regarding ASIC reverse engineering highlight the contrast between physically scanning dense chips and logically extracting netlists from layout files using standard industry tools. While generating a netlist from a layout is relatively straightforward, determining the actual functionality of the silicon remains the most significant hurdle. Participants also debated the practicalities of physical versus software-level hardware hacking, dismissing anecdotal claims of deducing digital logic opcodes using oscilloscopes as highly improbable.